1. K.N. Kim, J.Y. Lee, K.H. Lee, B.H. Noh, S.W. Nam, Y.S. Park, Y.H. Kim, H.S. Kim, J.S. Kim, J.K. Park, K.P. Lee, K.Y. Lee, J.T. Moon, J.S. Choi, J.W. Park, J.G. Lee, Highly manufacturable 1-Gb SDYNAMIC RAM, in VLSI Technology Digest of Technical Papers, June 1997, pp. 9–10
2. G. Bronner, H. Aochi, M. Gall, J. Gambino, S. Gernhardt, E. Hammerl, H. Ho, J. Iba, H. Ishiuchi, M. Jaso, R. Kleinhenz, T. Mii, M. Narita, L. Nesbit, W. Neumueller, A. Nitayama, T. Ohiwa, S. Parke, J. Ryan, T. Sato, H. Takato, S. Yoshikawa, A fully planarized 0.25-m CMOS technology for 256-Mbit DYNAMIC RAM and beyond, in VLSI Technology Digest of Technical Papers, June 1995, pp. 15–16
3. K. Itoh, R. Hori, H. Masuda, Y. Kamigaki, H. Kawamoto, H. Katto, A 5-V-only 64-K dynamic RAM, in ISSCC Digest of Technical Papers, Feb 1980, pp. 228–229
4. Y.-B. Kim, T.W. Chen, Assessing merged DYNAMIC RAM/logic technology. Integr. VLSI J. 27, 179–194 (1999)
5. P.M. Kogge, T. Sunaga, H. Miyataka, K. Kitamura, Combined DYNAMIC RAM and logic chip for massively parallel systems, in Proceedings of 16th Conference on Advanced Research in VLSI, Mar 1995, pp. 4–16