A Novel March XR Algorithm, Design, and Test Architecture for Memories-Reference-Cited by-同舟云学术

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A Novel March XR Algorithm, Design, and Test Architecture for Memories

Published:2022 Issue: Volume: Page:321-329
ISSN:1876-1100
Container-title:Lecture Notes in Electrical Engineering
language:
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Author:

Matri I. G.,Aishwaraya ,Shreya N.,Siddamal Saroja V.,Budihal Suneeta V.

Publisher

Springer Nature Singapore

Link

https://link.springer.com/content/pdf/10.1007/978-981-19-1111-8_26

Reference12 articles.

1. John PK, Rony Antony P (2017) BIST architecture for multiple RAMs in SoC. Procedia Comput Sci 115:159–165. ISSN 1877-0509, https://doi.org/10.1016/j.procs.2017.09.121

2. Wu Y, Ivanov A (2006) Low power SoC memory BIST. In: 2006 21st IEEE international symposium on defect and fault tolerance in VLSI systems, Arlington, VA, USA, pp 197–205. https://doi.org/10.1109/DFT.2006.39

3. Sargsyan D (2017) ISO 26262 compliant memory BIST architecture. In: 2017 computer science and information technologies (CSIT), Yerevan, Armenia, pp 78–82.https://doi.org/10.1109/CSITechnol.2017.8312145

4. Singh A, Kumar GM, Aasti A (2020) Controller architecture for memory BIST algorithms. In: 2020 IEEE international students’ conference on electrical, electronics and computer science (SCEECS), Bhopal, India, pp 1–5. https://doi.org/10.1109/SCEECS48394.2020.43

5. Patil SR, Musle DB (2017) Implementation of BIST technology for fault detection and repair of the multi-ported memory using FPGA. In: 2017 international conference of electronics, communication and aerospace technology (ICECA), Coimbatore, India, pp 43–47.https://doi.org/10.1109/ICECA.2017.8212849

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Novel March WY Approach for Dynamic Fault Detection in Memory BIST;2023 IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC);2023-12-18

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