Design of Low Power High Speed 2nd Order Discrete Time Sigma-Delta Modulator Using Charge Shared Double Tail Dynamic Comparator
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Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-99-0973-5_37
Reference14 articles.
1. Vikrant V, Nagaria RK (2020) Design and analysis of ultra high-speed low-power double tail dynamic comparator using charge sharing scheme. AEU—Int J Electr Commun 116:153068, ISSN 1434-8411. https://doi.org/10.1016/j.aeue.2020.153068
2. Qazi F, Dąbrowski JJ (2015) Passive SC sigma delta modulators revisited: analysis and design study. IEEE J Emerg Sel Top Circ Syst 5(4):624–637. https://doi.org/10.1109/JETCAS.2015.2502169
3. Pena-Perez A, Bonizzoni E, Maloberti F (2012) A 88-dB DR, 84-dB SNDR very low-power single op-amp third-order $\Sigma \Delta$ Modulator. IEEE J Solid-State Circ 47(9):2107–2118. https://doi.org/10.1109/JSSC.2012.2199669
4. Yang Z, Yao L, Lian Y (2012) A 0.5-V 35-μ \mu W 85-dB DR double-sampled ΔΣ\Delta\Sigma modulator for audio applications. IEEE J Solid-State Circ 47(3):722–735. https://doi.org/10.1109/JSSC.2011.2181677
5. Kim MG et al (2008) A 0.9 V 92 dB double-sampled switched-RC delta-sigma audio ADC. IEEE J Solid-State Circ 43(5):1195–1206. https://doi.org/10.1109/JSSC.2008.920329
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