1. Padma Sravani, A., and M. Satyam. 2011. Built-in self repair for SRAM array using redundancy. Proceedings of ACEEE International Journal on Communication 2(1): 18–21.
2. Pavlov, A., M. Sachdev, and J. Pineda de Gyvez. 2004. A SRAM weak cell fault model and a DFT technique with a programmable detection threshold. In ITC’04, pp. 1006–1015.
3. Harutyunyan, G., A. Hakhumyan, S. Shoukourian, V. Vardanian, and Y. Zorian. 2011. Symmetry measure for memory test and its application in BIST optimization. Journal of Electronic Testing 27 (6): 753–766.
4. Patrick, G., O. Heron, S. Pravossoudovitch, and M. Renovell. 2006. An efficient BIST architecture for delay faults in the logic cells of symmetrical SRAM-based FPGAs. Journal of Electronic Testing 22 (2): 161–172.
5. Shubhankar, Majumdar, and Prashant P. Bansod. 2014. Hardwired BIST architecture of SRAM. In Annual IEEE India Conference.