Network-on-Chip Aware Task Mappings
Author:
Publisher
Springer Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-15-8135-9_10
Reference21 articles.
1. Liu, W., et al.: Thermal-aware task mapping on dynamically reconfigurable network-on-chip based multiprocessor system-on-chip. IEEE Trans. Comput. 67(12), 1818–1834 (2018)
2. Kahng, A.B., Li, B., Peh, L., Samadi, K.: Orion 2.0: a fast and accurate NoC power and area model for early-stage design space exploration, pp. 423–428 (2009)
3. Wu, C., et al.: An efficient application mapping approach for the co-optimization of reliability, energy, and performance in reconfigurable NoC architectures. IEEE Trans. Comput. Aid. Des. Integr. Circ. Syst. 34(8), 1264–1277 (2015)
4. Chen, L., Zhu, D., Pedram, M., Pinkston, T.M.: Power punch: towards non-blocking power-gating of NoC routers, pp. 378–389 (2015)
5. Chou, C., Ogras, U.Y., Marculescu, R.: Energy- and performance-aware incremental mapping for networks on chip with multiple voltage levels. IEEE Trans. Comput. Aid. Des. Integr. Circ. Syst. 27(10), 1866–1879 (2008)
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