1. E.M. Davis, W.E. Harding, R.S. Schwartz, et al., Solid logic technology: Versatile, high-performance microelectronic. IBM J. Res. Dev. 8(2), 102–114 (1964)
2. A. Long, J. Xin, C.M. Lai, J. Chen, Y. Gao, et al., Pillar bump technology and integrated embedded passive devices, in 7th International Conference on Electronic Packaging Technology, (2006), pp. 1–5
3. J-STD-012, Implementation of Flip Chip and Chip Scale Technology (IPC, 1996)
4. Wang Z, Cheng L, Gao P,et al. CSP technology and its development foreground. Semiconductor Technol., 2003, 28(12): 39–43
5. M. Dreiza, A. Yoshida, J. Micksch, et al., Guidelines for the design of PoP (package-on-package). China Integrated Circuits 12, 61–65 (2005)., 60