Analysis of NBTI Impact on Clock Path Duty Cycle Degradation-Reference-Cited by-同舟云学术

Analysis of NBTI Impact on Clock Path Duty Cycle Degradation

Published:2022 Issue: Volume: Page:539-549
ISSN:2367-3370
Container-title:Cognitive Informatics and Soft Computing
language:
Short-container-title:

Author:

Ramkrishna Naik Kranti,Deshpande Abhay

Publisher

Springer Nature Singapore

Link

https://link.springer.com/content/pdf/10.1007/978-981-16-8763-1_44

Reference13 articles.

1. Goel N, Joshi K, Mukhopadhyay S, Nanaware N, Mahapatra S (2014) A comprehensive modeling framework for gate stack process dependence of DC and AC NBTI in SiON and HKMG p-MOSFETs. Microelectron Reliab 54. https://doi.org/10.1016/j.microrel.2013.12.017. Clerk Maxwell J (1892) A treatise on electricity and magnetism, 3rd edn. Clarendon, Oxford, vol 2, pp 68–73

2. Kang K, Kufluoglu H, Roy K, Ashraful Alam M (2007) Impact of negative-bias temperature instability in nanoscale SRAM array: modeling and analysis. IEEE Trans Comput-Aided Des Integr Circuits Syst 26(10):1770–1781. https://doi.org/10.1109/TCAD.2007.896317

3. Pachito J, Martins CV, Semião J, Santos M, Teixeira IC, Teixeira JP (2012) The influence of clock-gating on NBTI-induced delay degradation. In: 2012 IEEE 18th international on-line testing symposium (IOLTS), pp 61–66. https://doi.org/10.1109/IOLTS.2012.6313842

4. Bhardwaj S, Wang W, Vattikonda R, Cao Y, Vrudhula S (2006)Predictive modeling of the NBTI effect for reliable design. In: IEEE custom integrated circuits conference 2006, San Jose, CA, USA, pp 189–192. https://doi.org/10.1109/CICC.2006.320885

5. Kumar SV, Kim CH, Sapatnekar SS (2006) Impact of nbti on sram read stability and design for reliability. In: Proceedings of international symposium on quality electronic design