A full-transistor fine-grain multilevel delay element with compact regularity layout-Reference-Cited by-同舟云学术

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A full-transistor fine-grain multilevel delay element with compact regularity layout

Published:2020-02-03 Issue:1 Volume:103 Page:163-172
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Liu Bo^ORCID,Huang Zhi-hui^ORCID,Zhang Jin-can^ORCID,Liu Min^ORCID,Meng Qing-duan^ORCID

Funder

National Natural Science Foundation of China

Key Scientific Research Projects of Higher Education Institutions in Henan Province

Foundation of Department of Science and Technology of Henan Province

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s10470-020-01588-y.pdf

Reference20 articles.

1. Zhang, G. L., Li, B., Shi, Y., Hu, J., & Schlichtmann, U. (2018). EffiTest2: Efficient delay test and prediction for post-silicon clock skew configuration under process variations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,38(4), 705–718.

2. Singhvi, A., Moreira, M. T., Tadros, R. N., Calazans, N. L. V., & Beerel, P. A. (2016). A fine-grain, uniform, energy-efficient delay element for 2-phase bundled-data circuits. ACM Journal on Emerging Technologies in Computing Systems,13(2), 1–23.

3. Yang, J., Chao, C., & Lin, S. (2006). Tunable delay element for low power VLSI circuit design. In TENCON—IEEE region 10 conference 2006. https://doi.org/10.1109/TENCON.2006.344092.

4. Moon, B. M., Park, Y. J., & Jeong, D. K. (2008). Monotonic wide-range digitally controlled oscillator compensated for supply voltage variation. IEEE Transactions on Circuits and Systems II: Express Briefs,55(10), 1036–1040.

5. Heck, G., Heck, L. S., Singhvi, A., Moreira, M. T., Beerel, P. A., Calazans, N. L. V., et al. (2015). Analysis and optimization of programmable delay elements for 2-phase bundled-data circuits. In 2015 28th international conference on VLSI design. https://doi.org/10.1109/VLSID.2015.60.

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