Hardware-friendly HEVC motion estimation: new algorithms and efficient VLSI designs targeting high definition videos

Author:

Sanchez Gustavo,Zatt Bruno,Porto Marcelo,Agostini Luciano

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Reference26 articles.

1. JVT, Wiegand, T., Sullivan, G., & Luthra, A. (Ed.). (2003). Draft ITU-TRecommendation and final draft international standard of joint video specification (ITU-T Rec.H.264|ISO/IEC 14496-10 AVC).

2. JCT. (2011). Working Draft 3 of high-efficiency video coding. JCTVC-E603.

3. Cheng, Y., et al. (2009). An H.264 spatio-temporal hierarchical fast motion estimation algorithm for high-definition video. IEEE International Symposium on Circuits and Systems (ISCAS), 2009, 880–883.

4. Kuhn, P. (1999). Algorithms, complexity analysis and VLSI architectures for MPEG-4 motion estimation (Vol. 2). Amsterdam: Kluwer Academic Publishers.

5. Bhaskaran, V., & Konstantinides, K. (1999). Image and video compression standards: Algorithms and architectures (2nd ed.). Boston: Kluwer Academic Publishers.

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