FPGA implementation of high performance image de-noising filter
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
https://link.springer.com/content/pdf/10.1007/s10470-023-02208-1.pdf
Reference26 articles.
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2. Alexey, L. (2011). A SIMD cellular processor array vision chip with asynchronous processing capabilities. IEEE Transactions on Circuits and Systems I: Regular Papers, 58(10), 2420–2431. https://doi.org/10.1109/TCSI.2011.2131370
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4. Camunas-Mesa, A. J., Serrano-Gotarredona, T., & Linares-Barranco, B. (2012). An event-driven multi kernel filter processor module for event-driven vision sensors. IEEE Journal of Solid-State Circuits, 47(2), 504–517.
5. Liu, Z., Song, Y., Shao, M., Li, S., Li, L., Ishiwata, S., Nakagawa, M., Goto, S., & Ikenaga, T. (2009). HDTV1080p H.264/AVC encoder chip design and performance analysis. IEEE Journal of Solid-State Circuits, 44(2), 594–608.
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