Design and implementation of high performance and area efficient square architecture using Vedic Mathematics
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
http://link.springer.com/content/pdf/10.1007/s10470-019-01496-w.pdf
Reference22 articles.
1. Pihl, J., & Aas, E. J. (1996). A multiplier and squarer generator for high performance DSP applications. In Proceedings of the 39th Midwest symposium on circuits and systems, (Vol. 1, pp. 109–112).
2. Chen, T. C. (1971). A binary multiplication based on squaring. IEEE Transaction on Computers, 20(6), 678–680.
3. Pekmestzi, K. Z., Kalivas, P., & Moshopoulos, N. (2001). Long unsigned number systolic serial multipliers and squares. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 48(3), 316–321.
4. Dadda, L. (1985). Squares for binary numbers in serial form. In Proceedings of IEEE symposium on computer arithmetic (pp. 173–180).
5. Chaniotakis, E., Kalivas, P., & Pekmestzi, K. Z. (2005). Long number bit serial squares. In Proceedings of IEEE symposium on computer arithmetic (pp. 29–36).
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