Analysis of energy consumption bounds in CMOS current-steering digital-to-analog converters
-
Published:2022-03-26
Issue:3
Volume:111
Page:339-351
-
ISSN:0925-1030
-
Container-title:Analog Integrated Circuits and Signal Processing
-
language:en
-
Short-container-title:Analog Integr Circ Sig Process
Author:
Morales Chacón OscarORCID, Wikner J. Jacob, Svensson Christer, Siek Liter, Alvandpour Atila
Abstract
AbstractIn this paper, an attempt to estimate energy consumption bounds versus signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) in CMOS current-steering digital-to-analog converters is presented. A theoretical analysis is derived, including the design corners for noise, speed and linearity for the mixed-signal domain. The study is validated by comparing the theoretical results with published measured data. As result it serves as a design reference to aim for minimum energy consumption. It is found that for an equivalent number of bits (ENOBs), the noise-bound grows at a rate of 22ENOB, whereas the speed-bound increases by 2ENOB−2 and is dependent on device dimensions. Therefore, as the technology scales down, the noise bound will dominate, which is observed for an estimated SNR of about 40 dB in 65 nm CMOS process. The linearity bound is derived from an analysis based on the assumption of limited output impedance, where it is found to be dependent on the device dimensions and increase at a rate of 2ENOB−1. The observations show that it is possible to achieve less energy consumption in all the design corners for different SNR and SFDR specifications within the Nyquist frequency, fs/2.
Funder
VINNOVA The strategic research environment funded by the Swedish government Swedish Foundation for International Cooperation in Research and Higher Education Linköping University
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Reference41 articles.
1. Reza Rofougaran, A., Rofougaran, M., & Behzad, A. (2005). Radios next-generation wireless networks. IEEE Microwave Magazine, 6, 38–43. 2. Sadeghifar, M. R., Bengtsson, H., & Wikner, J. J. (2019). A voltage-mode RF DAC for massive MIMO system-on-chip digital transmitters. Analog Integr Circ Sig Process, 100, 683–692. 3. Huo, Y., Dong, X., & Xu, W. (2017). 5G cellular user equipment: From theory to practical hardware design. IEEE Access, 5, 13992–14010. 4. Ravinuthula, V., Bright, W., Weaver, M., Maclean, K., Kaylor, S., Balasubramanian, S., Dwobeng, E. (2016). A 14-bit 8.9 GS/s RF DAC in 40nm CMOS achieving > 71dBc LTE ACPR at 2.9 GHz. In 2016 IEEE symposium on VLSI circuits (VLSI-circuits) (pp. 1-2). 5. Lin, C. H., Wong, K. L. J., Kim, T. Y., Xie, G. R., Major, D., Unruh, G., Dommaraju, S.R., Eberhart, H., & Venes, A. (2018, February). A 16b 6GS/s Nyquist DAC with IMD <-90dBc up to 1.9 GHz in 16nm CMOS. In 2018 IEEE International Solid-State Circuits Conference-(ISSCC) (pp. 360-362).
Cited by
2 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
|
|