Author:
Hammerstrom Dan,Zaveri Mazad S.
Reference60 articles.
1. M.S. Zaveri, D. Hammerstrom, CMOL/CMOS implementations of Bayesian polytree inference: digital & mixed-signal architectures and performance/price. IEEE Trans. Nanotechnology 9(2), 194–211 (2010). DOI: 10.1109/TNANO.2009.2028342
2. D. Hammerstrom, M.S. Zaveri, Prospects for building cortex-scale CMOL/CMOS circuits: a design space exploration, in Proceedings of IEEE Norchip Conference (Trondheim, Norway, 2009)
3. C. Gao, D. Hammerstrom, Cortical models onto CMOL and CMOS – architectures and performance/price. IEEE Trans Circ. Syst-I 54, 2502–2515 (2007)
4. S. Borkar, Electronics beyond nano-scale CMOS, in Proceedings of 43rd Annual ACM/IEEE Design Automation Conf. (San Francisco, CA, 2006), pp. 807–808
5. R.I. Bahar, D. Hammerstrom, J. Harlow, W.H.J. Jr., C. Lau, D. Marculescu, A. Orailoglu, M. Pedram, Architectures for silicon nanoelectronics and beyond, IEEE Computer 40, 25–33 (2007)
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