1. EDCC-2 Companion Workshop on Dependable Computing: Workshop Proceedings. Silesian Technical University, Poland, 15 May 1996. ISBN 83-906582-1-6 (1997)
2. Moorthy, P., Bharathy, S.: An efficient test pattern generator for high fault coverage in built-in-self-test applications. In: IEEE Fourth International Conference on Computing, Communications and Networking Technologies, India (2013)
3. Liu, T., Liu, P., Liu, Y.: An efficient controlled LFSR hybrid BIST scheme. IEICE Electron. Express 15(8), 1–6 (2018)
4. Hławiczka, A., Badura, D.: Condensed circular self-test path: a low cost circular BIST. In: IEEE European Test Workshop—ETW’96, France (1996)
5. Devika, K.N., Bhakthavatchalu, R.: Design of reconfigurable LFSR for VLSI IC testing in ASIC and FPGA. In: International Conference on Communication and Signal Processing, pp. 928–932, India (2017)