Integration of partial scan and built-in self-test-Reference-Cited by-同舟云学术

Integration of partial scan and built-in self-test

Published:1995 Issue:1-2 Volume:7 Page:125-137
ISSN:0923-8174
Container-title:Journal of Electronic Testing
language:en
Short-container-title:J Electron Test

Author:

Lin Chih-Jen,Zorian Yervant,Bhawmik Sudipta

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering

Link

http://link.springer.com/content/pdf/10.1007/BF00993320.pdf

Reference34 articles.

1. E. Eichelberger and T.W. Williams, ?A Logic Design Structure for LSI Testability,?Proc. 14th Design Autom. Conf., pp. 462?468, June 1977.

2. E. Trischler, ?Incomplete Scan Path with an Automatic Test Generation Methodology,?Proc. Int'l. Test Conf., pp. 153?162, November 1980.

3. R. Gupta, R. Gupta, and M. Breuer, ?The BALLAST Methodology for Structure Partial Scan design,?IEEE Trans. on Comput., Vol. 39, No. 4, pp. 538?544, April 1990.

4. K.T. Cheng and V.D. Agrawal, ?A Partial Scan Method for Sequential Circuits with Feedbacks,?IEEE Trans. on Comput., Vol. 39, No. 4, pp. 544?548, April 1990.

5. D. Lee and S. Reddy, ?On Determining Scan Flip-flops in Partial Scan Designs,?Proc. Int'l. on f. on Computer Aided Design, pp. 322?325, November 1990.

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