Author:
Kan Tsang-Chi,Ruan Shanq-Jang,Chang Ting-Feng,Yang Shih-Hsien
Publisher
Springer Science and Business Media LLC
Subject
Applied Mathematics,Signal Processing
Reference31 articles.
1. R. Aitken, Dfm metrics for standard cells, in IEEE International Symposium on Quality Electronic Design (ISQED) (2006), pp. 490–496
2. Y. Ban, C. Choi, H. Shin, Y. Kang, W.H. Paik, Analysis and optimization of process-induced electromigration on signal interconnects in 16nm FinFET SoC (system-on-chip), in SPIE Advanced Lithography, Design-Process-Technology Co-optimization for Manufacturability VIII (2014), p. 90530P
3. Y. Ban, J. Sweis, P. Hurat, Y.C. Lai, Y. Kang, W.H. Paik, W. Xu, H. Song, Layout Induced Variability and Manufacturability Checks in FinFETs Process, in SPIE Advanced Lithography, Design-Process-Technology Co-optimization for Manufacturability VIII (2014), p. 90530I
4. T.F. Chang, T.C. Kan, S.H. Yang, S.J. Ruan, Enhanced redundant via insertion with multi-via mechanisms, in IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (2011), pp. 218–223
5. H.Y. Chen, M.F. Chiang, Y.W. Chang, L. Chen, B. Han, Full-chip routing considering double-via insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 844–857 (2008)
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