High-Speed and Area-Efficient Modified Binary Divider-Reference-Cited by-同舟云学术

High-Speed and Area-Efficient Modified Binary Divider

Published:2022-01-30 Issue:6 Volume:41 Page:3350-3371
ISSN:0278-081X
Container-title:Circuits, Systems, and Signal Processing
language:en
Short-container-title:Circuits Syst Signal Process

Author:

Pazhani A. Azhagu Jaisudhan,Samuel T. S. Arun

Publisher

Springer Science and Business Media LLC

Subject

Applied Mathematics,Signal Processing

Link

https://link.springer.com/content/pdf/10.1007/s00034-021-01937-w.pdf

Reference16 articles.

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2. S. Amanollahi, G. Jaberipur, Energy-efficient VLSI realization of binary64 division withRedundant number systems. IEEE Trans. Very Large Scale Integr. Syst. 25(3), 954–961 (2017)

3. E. Antelo, T. Lang, P. Montuschi, A. Nannarelli, Digit-recurrence dividers with reduced logical depth. IEEE Trans. Comput. 54(7), 837–851 (2005)

4. T.M. Carter, J.E. Robertson, Radix-16 signed-digit division. IEEE Trans. Comput. 39(12), 1424–1433 (1990)

5. L. Chen, J. Han, W. Liu, P. Montuschi, F. Lombardi, Design, evaluation and application of approximate high-radix dividers. IEEE Trans. Multi Scale Comput. Syst. 4(3), 299–312 (2018)

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