Compact Modeling of Fin-LDMOS Transistor Based on the Surface Potential
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electronic, Optical and Magnetic Materials
Link
http://link.springer.com/article/10.1007/s12633-019-00118-4/fulltext.html
Reference23 articles.
1. Wei J, Luo X, Ma D, Wu J, Li Z, Zhang B (2016) Accumulation mode triple gate SOT LDMOS with ultralow on-resistance and enhanced transconductance. Proceedings of the 28th international symposium on power semiconductor devices and ICs (ISPSD)
2. Cheng S, Fang D, Qiao M, Zhang S, Zhang G, Gu Y, He Y, Zhou X, Qi Z, Li Z, Zhang B, Novel A (2017) 700V deep trench isolated double RESURF LDMOS with P-sink layer. Proceedings of the 29th international symposium on power semiconductor devices & ICs
3. Qiao M, Wang Z, Wang Y, Yu L, Xiao Q, Li Z, Zhang B (2017) 3-D edge termination design and RON,sp-BV model of A 700-V triple RESURF LDMOS with N-type top layer. IEEE Trans Electron Devices 64(6):2579–2586
4. Ge W, Luo X, Wu J, Lv M, Wei J, Ma D, Deng G, Cui W, Yang Y, Zhu K (2017) Ultra-low on-resistance LDMOS with multi-plane electron accumulation layers. IEEE Electron Device Lett 38(7):910–913
5. Saremi M, Ebrahimi B, Afzali-Kusha A, Mohammadi S (2011) A partial-SOI LDMOSFET with triangle buried-oxide for breakdown voltage improvement. Microelectron Reliab 51(12):2069–2076
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