An Analytical Model Including Interface Traps and Temperature Effects in Negative Capacitance Double Gate Field Effect Transistor
Author:
Funder
Education exploratory reform project
Publisher
Springer Science and Business Media LLC
Subject
Electronic, Optical and Magnetic Materials
Link
https://link.springer.com/content/pdf/10.1007/s12633-020-00643-7.pdf
Reference27 articles.
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2. Gaidhane AD, Pahwa G, Verma A, Chauhan YS (2018) Compact modeling of drain current, charges, and capacitances in long-channel gate-all-around negative capacitance MFIS transistor. IEEE Transactions on Electron Devices 65(5):2024–2032. https://doi.org/10.1109/TED.2018.2813059
3. You WX, Su P (2017) Design space exploration considering back-gate biasing effects for 2D negative-capacitance field-effect transistors. IEEE Transactions on Electron Devices 64 (8):3476–3481. https://doi.org/10.1109/TED.2017.2714687
4. Bansal M, Kaur H (2018) Impact of negative capacitance effect on germanium double gate pFET for enhanced immunity to interface trap charges. Superlattices and Microstructures 117:189–199. https://doi.org/10.1016/j.spmi.2018.03.001
5. Peng Y, Han G, Chen Z, Li Q, Zhang J, Hao Y (2018) Analytical calculation of influence of ferroelectric properties on electrical characteristics negative capacitance germanium FETs. IEEE Journal of the Electron Devices Society 6(1):233–239. https://doi.org/10.1109/JEDS.2018.2794069
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