Design Considerations and Optimization of Electrostatic Doped Ferroelectric Nanotube Tunnel FET: Analog and Noise Analysis
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electronic, Optical and Magnetic Materials
Link
https://link.springer.com/content/pdf/10.1007/s12633-022-01720-9.pdf
Reference38 articles.
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3. Riel H, Wernersson LE, Hong M, Del Alamo JA (2014) III–V compound semiconductor transistors—from planar to nanowire structures. Mrs Bulletin 39(8):668–677. https://doi.org/10.1557/mrs.2014.137
4. Chen FW, Ilatikhameneh H, Klimeck G, Chen Z, Rahman R (2016) Configurable electrostatically doped high performance bilayer graphene tunnel FET. IEEE Journal of the Electron Devices Society 4(3):124–128
5. Kumar N, Raman A (2019) Performance Assessment of the charge-plasma-based cylindrical GAA Vertical nanowire TFET with Impact of interface trap charges. IEEE Trans Electron Devices 66(10):4453–4460
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