IF: A Validation Environment for Timed Asynchronous Systems-Reference-Cited by-同舟云学术

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IF: A Validation Environment for Timed Asynchronous Systems

Published:2000 Issue: Volume: Page:543-547
ISSN:0302-9743
Container-title:Computer Aided Verification
language:
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Author:

Bozga Marius,Fernandez Jean-Claude,Ghirvu Lucian,Graf Susanne,Krimm Jean-Pierre,Mounier Laurent

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/10722167_41

Reference22 articles.

1. Telelogic AB. SDT Reference Manual, http://www.telelogic.se

2. Lecture Notes in Computer Science;S. Bensalem,1998

3. Lecture Notes in Computer Science;S. Bornot,1998

4. Lecture Notes in Computer Science;D. Bošnački,2000

5. Lecture Notes in Computer Science;M. Bozga,1999

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2. An evaluation of timed scenario notations;Journal of Systems and Software;2010-02

3. VeriTech: a framework for translating among model description notations;International Journal on Software Tools for Technology Transfer;2006-07-11

4. Evaluating the Effectiveness of Slicing for Model Reduction of Concurrent Object-Oriented Programs;Tools and Algorithms for the Construction and Analysis of Systems;2006

5. An Expressive and Implementable Formal Framework for Testing Real-Time Systems;Lecture Notes in Computer Science;2005

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