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3. A.L. DeCegama, “The Technology of Parallel Processing”Parallel Processing Architectures and VLSI Hardware, Vol. I, Prentice Hall, Englewood Cliffs, New Jersey, 1989.
4. S.Y. Kung,VLSI Array Processors, Prentice-Hall, 1988.
5. H.T. Kung and M.S. Lam, “Fault-Tolerance and Two Level Pipelining in VLSI Systolic Arrays,”MIT Conference on Advanced Research in VLSI, pp. 74–83, Jan. 1984.