Design of the PSC: A Programmable Systolic Chip-Reference-Cited by-同舟云学术

Design of the PSC: A Programmable Systolic Chip

Published:1983 Issue: Volume: Page:287-302
ISSN:
Container-title:Third Caltech Conference on Very Large Scale Integration
language:
Short-container-title:

Author:

Fisher Allan L.,Kung H. T.,Monier Louis M.,Walker Hank,Dohi Yasunori

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/978-3-642-95432-0_17.pdf

Reference22 articles.

1. Barbacci, M.R. Instruction Set Processor Specifications (ISPS): The Notation and Its Application. IEEE Transactions on Computers January, 1981.

2. Bayer, R. and Haerder, T. Preplanning of Disk Merges. Computing 21(1): 1–16, 1978.

3. Brent, R.P. and Kung, H.T. Systolic VLSI Arrays for Polynomial GCD Computation, Technical Report, Carnegie-Mellon University, Computer Science Department, May, 1982.

4. Cohen, D. and Tyree, V. Quality Control from die Silicon Broker’s Perspective. VLSI Design III(4):24–30, July/August, 1982.

5. Dowell, R., Newton, A.R. and Pederson, D.O. SPICE VAX User’s Guide. Department of Electrical Engineering and Computer Science, U. C. Berkeley.

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1. Design and Programming of Systolic Array Cells for Signal Processing;VLSI Signal Processing Technology;1994

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4. Minimum-diameter cyclic arrangements in mapping data-flow graphs onto VLSI arrays;Mathematical Systems Theory;1988-12

5. The architecture of a Linda coprocessor;ACM SIGARCH Computer Architecture News;1988-05-17