High Speed BCD Adder

Author:

Sundaresan C.,Chaitanya C. V. S.,Venkateswaran P. R.,Bhat Somashekara,Mohan Kumar J.

Publisher

Springer Berlin Heidelberg

Reference13 articles.

1. Buchholz, W.: Fingers or Fists? (The Choice of Decimal or Binary Representation). Communications of the ACM 2(12), 3–11 (1959)

2. Cowlishaw, M.F.: Decimal Floating-Point: Algorism for Computers. In: Proceedings of 16th IEEE Symposium onComputer Arithmetic, pp. 104–111 (June 2003)

3. Kenney, R.D., Schulte, M.J.: Multioperand Decimal Addition. In: Proc. IEEE CS Ann. Symp. VLSI, pp. 251–253 (February 2004)

4. Kenney, R.D., Schulte, M.J.: High-speed multioperand decimal adders. IEEE Transactions on Computers 54(8), 953–963 (2005)

5. Erle, M.A., Schulte, M.J.: Decimal Multiplication via Carry-Save Addition. In: Proc. IEEE 14th Int’l Conf. Application-Specific Systems, Architectures, and Processors, pp. 348–358 (June 2003)

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1. A Fast FPGA-Based BCD Adder;Circuits, Systems, and Signal Processing;2018-02-20

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