Gate Sizing
Author:
Publisher
Springer Berlin Heidelberg
Link
http://link.springer.com/content/pdf/10.1007/978-3-642-27848-8_159-2
Reference15 articles.
1. Chen CP, Chu CN, Wong DF (1998) Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. In: Proceedings of the 1998 IEEE/ACM international conference on computer-aided design, San Jose, pp 617–624
2. Chen HY, Kang SM (1991) iCOACH: a circuit optimization aid for CMOS high-performance circuits. Intergr VLSI J 10(2):185–212
3. Conn AR, Coulman PK, Haring RA, Morrill GL, Visweshwariah C, Wu CW (1998) Jiffy Tune: circuit optimization using time-domain sensitivities. IEEE Trans Comput Aided Des Intergr Circuits Syst 17(12):1292–1309
4. Cormen TH, Leiserson CE, Rivest RL (1990) Introduction to algorithms. McGraw-Hill, New York
5. Dai Z, Asada K (1989) MOSIZ: a two-step transistor sizing algorithm based on optimal timing assignment method for multi-stage complex gates. In: Proceedings of the 1989 custom integrated circuits conference, New York, pp 17.3.1–17.3.4
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