A Generalized Power Reduction Technique for Truncated Multiplier via Latching the Data Inputs and Error Compensating Carry-Reference-Cited by-同舟云学术

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A Generalized Power Reduction Technique for Truncated Multiplier via Latching the Data Inputs and Error Compensating Carry

Published:2023-09-14 Issue: Volume: Page:
ISSN:2228-6179
Container-title:Iranian Journal of Science and Technology, Transactions of Electrical Engineering
language:en
Short-container-title:Iran J Sci Technol Trans Electr Eng

Author:

Joshi Pankaj U.^ORCID,Deshmukh R. B.

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Computer Networks and Communications,Computer Vision and Pattern Recognition,Energy Engineering and Power Technology,Signal Processing

Link

https://link.springer.com/content/pdf/10.1007/s40998-023-00658-x.pdf

Reference19 articles.

1. Chang CH, Satzoda RK (2010) A low error and high performance multiplexer-based truncated multiplier. IEEE Trans Very Large Scale Integr Syst 18(12):1767–1771

2. Chen KH, Chu YS (2009) A spurious-power suppression technique for multimedia/DSP applications. IEEE Trans Circuits Syst I Regul Pap 56(1):132–143

3. Chen OT-C, Wang S, Wu YW (2003) Minimization of switching activities of partial products for designing low-power multipliers. IEEE Trans Very Large Scale Integr Syst 11(3):418–433

4. De Caro D, Petra N, Strollo AG, Tessitore F, Napoli E (2013) Fixed-width multipliers and multipliers-accumulators with min–max approximation error. IEEE Trans Circuits Syst I Regul Pap 60(9):2375–2388

5. ECG Data Base (2000) ECG Data Base is available for download from https://doi.org/10.13026/C2G01T

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