Impact of Back Gate Bias on Analog Performance of Dopingless Transistor
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
https://link.springer.com/content/pdf/10.1007/s42341-022-00426-4.pdf
Reference30 articles.
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3. N. Kamal, M. Panchore, J. Singh, 3-D simulation of junction- and doping-free field-effect transistor under heavy ion irradiation. IEEE Trans. Device Mater. Reliab. 18(2), 173–179 (2018). https://doi.org/10.1109/TDMR.2018.2811493
4. M. Ehteshamuddin, S.A. Loan, M. Rafat, Planar junctionless silicon-on-insulator transistor with buried metal layer. IEEE Electron Device Lett. 39(6), 799–802 (2018). https://doi.org/10.1109/LED.2018.2829915
5. T. Ohrou, N. Sugii, T. Hiramoto, Impact of parameter variations and random dopant fluctuations on short-channel fully depleted SOI MOSFETs with extremely thin BOX. IEEE Electron Device Lett. 28(8), 740–742 (2007). https://doi.org/10.1109/LED.2007.901276
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