Early-Stage Definition of LPX: A Low Power Issue-Execute Processor-Reference-Cited by-同舟云学术

Early-Stage Definition of LPX: A Low Power Issue-Execute Processor

Published:2003 Issue: Volume: Page:1-17
ISSN:0302-9743
Container-title:Power-Aware Computer Systems
language:
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Author:

Bose P.,Brooks D.,Buyuktosunoglu A.,Cook P.,Das K.,Emma P.,Gschwind M.,Jacobson H.,Karkhanis T.,Kudva P.,Schuster S.,Smith J.,Srinivasan V.,Zyuban V.,Albonesi D.,Dwarkadas S.

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/3-540-36612-1_1

Reference27 articles.

1. D. H. Albonesi. The inherent energy efficiency of complexity-effective processors. In Power-Driven Microarchitecture Workshop at ISCA25, June 1998.

2. D.H. Albonesi. Selective cache ways: on-demand cache resource allocation. In Proceedings of the 32nd International Symposium on Microarchitecture (MICRO-32), pages 248–259, Nov. 1999.

3. C. Anderson et al. Physical design of a fourth-generation power ghz microprocessor. In ISSCC Digest of Technical Papers, page 232, 2001.

4. R. Balasubramonian, D. Albonesi, A. Buyuktosunoglu, and S. Dwarkadas. Memory hierarchy reconfiguration for energy and performance in general purpose architectures. In Proceedings of the 33rd International Symposium on Microarchitecture (MICRO-33), pages 245–257, Dec. 2000.

5. A. Baniasadi and A. Moshovos. Instruction flow-based front-end throttling for power-aware high performance processors. In Proceedings of International Symposium on Low Power Electronics and Design, August 2001.

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