Fault-Tolerant Routing Algorithms in Networks On-Chip-Reference-Cited by-同舟云学术

Fault-Tolerant Routing Algorithms in Networks On-Chip

Published:2013-09-25 Issue: Volume: Page:193-210
ISSN:
Container-title:Routing Algorithms in Networks-on-Chip
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Author:

Behrouz Reyhaneh Jabbarvand,Modarressi Mehdi,Sarbazi-Azad Hamid

Publisher

Springer New York

Link

http://link.springer.com/content/pdf/10.1007/978-1-4614-8274-1_8

Reference19 articles.

1. ITRS, International technology roadmap for semiconductors (2007 edition), http://public.itrs.net

2. D. Sylvester, K. Keutzer, A global wiring paradigm for deep submicron design. IEEE Trans. Comp. Aid. Des. Integ. Circuit. Syst. 19(2), 242–252 (2000)

3. A. Alaghi, M. Sedghi, N. Karimi, M. Fathy, Z. Navabi, Reliable NoC architecture utilizing a robust rerouting algorithm, in Proceedings of the 6th IEEE East–West Design and Test Symp. (EWDTS) (Kharkov, Poland, 2008), pp. 101–105

4. A. Patooghy, S.G. Miremadi, XYX: A power & performance efficient fault-tolerant routing algorithm for network on chip, in Proceedings of the 17th EuroMicro International Conference on Parallel, Distributed and Networks-Based Processing (Weimar, Germany, 2009), pp. 245–251

5. C. Constantinescu, Intermittent faults in VLSI circuits, in Proceedings of IEEE Workshop on System Effects of Logic Sot Errors, Urbana-Champaign, USA, 2006

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