1. Abramovici, M., Menon, P. R., and Miller, D. J. (1984). Critical path tracing: An alternative to fault simulation. IEEE Design and Test, 1:93–93.
2. Ashar, P., Ghosh, A., Devadas, S., and Newton, A. (1991). Combinational and sequential logic verification using general binary decision diagrams. In Proceedings of the International Workshop on Logic Synthesis.
3. Berglez, F., Pownall, P., and Humm, R. (1985). Accelerated ATPG and fault grading via testability analysis. In International Symposium on Circuits and Systems, pages 695–698. IEEE.
4. Berglez, E, Bruan, D., and Kozminski, K. (1989). Combinational profiles of sequential benchmark circuits. In International Symposium on Circuits and Systems, pages 1929–1934. IEEE.
5. Berman, C. and Trevillyan, H. (1989). Functional comparison of logic designs for VLSI chips. In Proceedings of the IEEE International Conference on Computer-Aided Design, pages 456–459, Santa Clara, CA. IEEE.