Matrix Multiplication on Digital Signal Processors and Hierarchical Memory Systems

Author:

Palacios Ismael,Medina Mario,Moreno Jaime

Publisher

Springer US

Reference8 articles.

1. E. A. Lee, Programmable DSP Architectures, Parts I & II, IEEE ASSP Magazine 4:19, October 1988; 4:11, January 1989.

2. M. Speiser and H. Whitehouse, A Review of Signal Processing with Systolic Arrays, in “SPIE Real-Time Processing Vi”, 2:6, August 1983.

3. K. A. Gallivan, R. J. Plemmons and A. H. Sameh, Parallel Algorithms for Dense Linear Algebra Computations, SIAM Review 54:135, March 1990.

4. J. J. Dongarra, J. Du Croz, S. Hammarling and I. Duff, A Set of Level 3 Basic Linear Algebra Subprograms, ACM Trans. Math. Softw., 1:17, March 1990.

5. P. Papamichalis and R. Simar, Jr., The TMS 320C30 Floating-Point Digital Signal Processor, IEEE Micro December 1990.

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