Fault and Fault Modelling
Publisher
Springer-Verlag
Reference45 articles.
1. H. Walker and S.W. Director, “VLASIC: a catastrophic fault yield simulator for integrated circuits”, IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, Vol. CAD-5, pp. 541–556, October 1986. 2. R.J.A. Harvey, A.M.D. Richardson, E.M.F.G. Bruls and K. Baker, “Analogue fault simulation based on layout dependent fault models”, Proceedings, 1994 IEEE International Test Conference, pp. 641–649, October 1994. 3. T. Olbrich, J. Perez, I.A. Grout, A.M.D. Richardson and C. Ferrer, “Defect-oriented vs schematic-level based fault simulation for mixed-signal ICs, Proceedings, 1996 IEEE International Test Conference, pp. 511–520, October 1996. 4. F. Fantini and C. Morandi, “Failure modes and mechanisms for VLSI ICs-a review”, IEE Proceedings-G, Circuits, Devices and Systems, Vol. 132, pp. 74–81, June 1985. 5. F. Jensen, Electronic Component Reliability, John Wiley & Sons Ltd., West Sussex, 1995.
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