Publisher
Springer International Publishing
Reference27 articles.
1. Dalt ND, Harteneck M, Sandner C, Wiesbauer A (2002) On the jit-ter requirements of the sampling clock for analog-to-digital converters. IEEE Trans Circuits Syst I 49:1354–1360
2. Limotyrakis S, Kulchycki SD, Su DK, Wooley BA (2005) A 150-MS/s 8-b 71-mW CMOS time-interleaved ADC. IEEE J Solid-State Circuits 40:1057–1067
3. van der Goes F, Ward CM, Astgimath S, Yan H, Riley J, Zeng Z, Mulder J, Wang S, Bult K (2014) A 1.5 mW 68 dB SNDR 80 Ms/s 2 interleaved pipelined SAR ADC in 28 nm CMOS. IEEE J Solid-State Circuits 49:2835–2845
4. Bult K, Geelen GJGM (1990) A fast-settling CMOS op amp for SC circuits with 90-dB DC gain. IEEE J Solid-State Circuits 25:1379–1384
5. Liu W, Chang y, Hsien S-K et al (2009) A 600 mW 30 mW 0.13 μm CMOS ADC array achieving over 60dB SFDR with adaptive digital equalization. In: International solid-state circuits conference, digest of technical papers, pp 82-83