Independent Gate Operation of NAND Flash Memory Device with Improved Retention Characteristics
Author:
Publisher
Springer International Publishing
Link
http://link.springer.com/content/pdf/10.1007/978-3-319-97604-4_88
Reference9 articles.
1. K.H. Jang et al., Self-amplified dual gate charge trap flash memory for low-voltage operation. IEEE Electron Device Lett. 34(6), 756–758 (June 2013)
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3. K. Miyaji, C. Hung, K. Takeuchi, Scaling trends and tradeoffs between short channel Effect and channel boosting characteristics in sub-20 nm bulk/silicon-on-insulator NAND flash memory. Jpn. J. Appl. Phys. 51, 04DD12 (Apr 2012)
4. S.J. Choi, D.II. Moon, S. Kim, J.-H. Ahn, J.-S. Lee, J.-Y. Kim, Y.-K. Choi, Nonvolatile memory by all-around-gate junctionless transistor composed of silicon nanowire on bulk substrate. IEEE Electron Device Lett. 32(5), 602–604 (May 2011)
5. Sentaurus TCAD Manuals, Synopsys Inc (Mountain view, CA, USA, 2016)
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