Architecture Virtualization for Run-Time Hardware Multithreading on Field Programmable Gate Arrays-Reference-Cited by-同舟云学术

Architecture Virtualization for Run-Time Hardware Multithreading on Field Programmable Gate Arrays

Published:2015 Issue: Volume: Page:167-178
ISSN:0302-9743
Container-title:Lecture Notes in Computer Science
language:
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Author:

Metzner Michael,Lizarraga Jesus A.,Bobda Christophe

Publisher

Springer International Publishing

Link

http://link.springer.com/content/pdf/10.1007/978-3-319-16214-0_14

Reference15 articles.

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2. Bjerregaard, T., Mahadevan, S.: A survey of research and practices of network-on-chip. ACM Comput. Surv. 38(1), June 2006

3. Brant, A., Lemieux, G.G.: Zuma: An open fpga overlay architecture. In: Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 93–96 (2012)

4. Christian Plessl, G., Platzner, M.: Hardware virtualization on dynamically reconfigurable processors. In: Khalgui, M., Hanisch, H.-M. (eds:) Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility. IGI Global (2011)

5. Dall’Osso, M., Biccari, G., Giovannini, L., Bertozzi, D., Benini, L.: xpipes: a latency insensitive parameterized network-on-chip architecture for multi-processor socs. In: Proceedings of the 21st International Conference on Computer Design, ICCD 2003, p. 536. IEEE Computer Society, Washington, DC (2003)

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