Simulations of Transport Characteristics of Core-Shell Nanowire Transistors with Electrostatic All-Around Gate
Author:
Publisher
Springer International Publishing
Link
http://link.springer.com/content/pdf/10.1007/978-3-319-44260-0_14
Reference15 articles.
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3. Fang, M., Han, N., Wang, F., Yang, Z.-X., Yip, S.P., Dong, G., Hou, J.J., Chueh, Y., Ho, J.C.: III-V nanowires: synthesis, property manipulations, and device applications. J. Nanomater. 2014, 1 (2014)
4. Tomioka, K., Yoshimura, M.: A III-V nanowire channel on silicon for high-performance vertical transistors. Nature 488, 189 (2012)
5. Hoobs, R., Holmes, J.: Semiconductor Nanowire Fabrication via Bottom-Up and Top-Down Paradigms (2011)
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