A Lost Cycles Analysis for Performance Prediction using High-Level Synthesis
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Publisher
Springer International Publishing
Link
http://link.springer.com/content/pdf/10.1007/978-3-319-30481-6_28
Reference7 articles.
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3. Park, J., et al.: Performance and area modeling of complete FPGA designs in the presence of loop transformations. IEEE Trans. Comput. 53(11), 1420–1435 (2004)
4. Zhong G., et al.: Design space exploration of multiple loops on FPGAs using high level synthesis. In: 32nd IEEE International Conference on Computer Design (ICCD), pp. 456–463. IEEE (2014)
5. Schafer, B.C., et al.: Divide and conquer high-level synthesis design space exploration. ACM Trans. Design Autom. Electron. Syst. (TODAES) 17(3), 29 (2012)
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1. Efficiency analysis methodology of FPGAs based on lost frequencies, area and cycles;Journal of Parallel and Distributed Computing;2018-03
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