Scan Design: Basics, Advancements, and Vulnerabilities-Reference-Cited by-同舟云学术

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Scan Design: Basics, Advancements, and Vulnerabilities

Published:2017 Issue: Volume: Page:107-126
ISSN:
Container-title:Hardware Security and Trust
language:
Short-container-title:

Author:

Saeed Samah Mohamed,Ali Sk Subidh,Sinanoglu Ozgur

Publisher

Springer International Publishing

Link

http://link.springer.com/content/pdf/10.1007/978-3-319-44318-8_6

Reference29 articles.

1. Bushnell M, Agrawal V. Essentials of electronic testing for digital. Memory and mixed-signal VLSI circuits. Springer; 2005.

2. Rajski J, Tyszer J, Kassab M, Mukherjee N, Thompson R, Tsai KH, et al. Embedded deterministic test for low cost manufacturing test. In: Proceedings of IEEE international test conference, 2002. p. 301–10.

3. Barnhart C, Brunkhorst V, Distler F, Farnsworth O, Keller B, Koenemann B. OPMISR: the foundation for compressed ATPG vectors. In: Proceedings of IEEE international test conference, 2001. p. 748–57.

4. Samaranayake S, Gizdarski E, Sitchinava N, Neuveux F, Kapur R, Williams TW. A reconfigurable shared scan-in architecture. In: Proceedings of IEEE VLSI test symposium, 2003. p. 9–14.

5. Touba NA. Survey of test vector compression techniques. IEEE Des Test Comput. 2006;23(4):294–303.

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1. Securing data in Wireless Sensor Network using Hybrid ECC + AES Cryptographic Approach;2023 International Conference on Innovative Computing, Intelligent Communication and Smart Electrical Systems (ICSES);2023-12-14

2. Node-Node Data Exchange in IoT Devices Using Twofish and DHE;Advances in Science, Technology and Engineering Systems Journal;2021-03

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