Design and Area Performance Energy Consumption Comparison of Secured Network-on-Chip with PTP and Bus Interconnections-Reference-Cited by-同舟云学术

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Design and Area Performance Energy Consumption Comparison of Secured Network-on-Chip with PTP and Bus Interconnections

Published:2022-05-30 Issue:5 Volume:103 Page:1479-1491
ISSN:2250-2106
Container-title:Journal of The Institution of Engineers (India): Series B
language:en
Short-container-title:J. Inst. Eng. India Ser. B

Author:

Jayshree ,Seetharaman Gopalakrishnan,Pati Debadatta

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,General Computer Science

Link

https://link.springer.com/content/pdf/10.1007/s40031-022-00735-5.pdf

Reference48 articles.

1. P. Babu. “Reconfigurable fpga architectures: A survey and applications.” J. Inst. Eng. India Ser. B (2020), (2020)

2. R.P.R. Das, N, “Detection of crosstalk faults in field programmable gate arrays (fpga),’’. J. Inst. Eng. India Ser. B 96, 227–236 (2015)

3. M.K. Meher, P, “Modifications in cmos dynamic logic style: A review paper,’’. J. Inst. Eng. India Ser. B 96, 391–399 (2015)

4. M. R, S. P, e a, B. Biswas, “An efficient vlsi architecture of the enhanced three step search algorithm,’’. J. Inst. Eng. India Ser. B 97, 303–309 (2016)

5. B. Liu, G. Qu, VLSI supply chain security risks and mitigation techniques: A survey. Integration 55, 438–448 (2016)

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3. Enhancing High-Speed Data Communications: Optimization of Route Controlling Network on Chip Implementation;IEEE Access;2024

4. A Comparative Study and Analysis of Various Interconnects for Very Large-Scale Integration;ECS Advances;2023-09-01

5. FPGA based Design and Simulation of basic Routing Protocols;2022 Fourth International Conference on Cognitive Computing and Information Processing (CCIP);2022-12-23

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