Design and Area Performance Energy Consumption Comparison of Secured Network-on-Chip with PTP and Bus Interconnections

Author:

Jayshree ,Seetharaman Gopalakrishnan,Pati Debadatta

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,General Computer Science

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Parallel Calculation of π in NoCs Using a Remote Testbed;2024 International Conference on Industrial Engineering, Applications and Manufacturing (ICIEAM);2024-05-20

2. Virtual Coordinate System Based on a Circulant Topology for Routing in Networks-On-Chip;Symmetry;2024-01-21

3. Enhancing High-Speed Data Communications: Optimization of Route Controlling Network on Chip Implementation;IEEE Access;2024

4. A Comparative Study and Analysis of Various Interconnects for Very Large-Scale Integration;ECS Advances;2023-09-01

5. FPGA based Design and Simulation of basic Routing Protocols;2022 Fourth International Conference on Cognitive Computing and Information Processing (CCIP);2022-12-23

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