Publisher
Springer Berlin Heidelberg
Reference35 articles.
1. Fischer, V., Gramain, F.: Resource sharing in a Rijndael implementation based on a new MixColumn and InvMixColymn relation. submitted to Electronic Letters, reference number: ELL 39 395, April 14 (2003)
2. Järvinen, K.U., Tommiska, M.T., Skyttä, J.O.: A fully pipelined memoryless 17.8 Gbps AES-128 encryptor. In: International Symposium on Field-Programmable Gate Arrays (FPGA 2003), Monterey, CA (2003)
3. Standaert, F.X., Rouvroy, G., Quisquater, J.J., Legat, J.D.: A methodology to implement block ciphers in reconfigurable hardware and its application to fast and compact AES RIJNDAEL. In: International Symposium on Field-Programmable Gate Arrays (FPGA 2003), Monterey, CA (2003)
4. Verbauwhede, I., Schaumont, P., Kuo, H.: Design and performance testing of a 2.29- GB/s rijndael processor. IEEE Journal of Solid-State Circuits 38(3) (March 2003)
5. Daemen, J., Rijmen, V.: The design of Rijndael: AES – The Advanced Encryption Standard. Springer, Heidelberg (2002) ISBN 3-540-42580-2
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