RTL Power Modeling and Estimation of Sleep Transistor Based Power Gating

Author:

Rosinger Sven,Helms Domenik,Nebel Wolfgang

Publisher

Springer Berlin Heidelberg

Reference12 articles.

1. Benini, L., De Micheli, G.: Dynamic Power Management. In: Design Techniques and CAD Tools, Kluwer Academic Publishers, Dordrecht (1998)

2. Pedram, M., Rabaey, J.: Power Aware Design Methodologies. Kluwer Academic Publishers, Dordrecht (2002)

3. Min, K.-S., Sakurai, T.: Zigzag Super Cut-off CMOS (ZSCCMOS) Scheme with Self-Saturated Virtual Power Lines for Subthreshold-Leakage-Suppressed Sub-1V-VDD LSI’s. In: Proceedings of the 28 th European Solid-State Circuits Conference, 2002, pp. 679–682 (2002)

4. Jiang, H., Marek-Sadowska, M., Nassif, S.R.: Benefits and Costs of Power-Gating Technique. In: Proceedings of the 2005 International Conference on Computer Design, 2005, pp. 559–566 (2005)

5. Kao, J., Chandrakasan, A., Antoniadis, D.: Transistor sizing issues and tool for multithreshold CMOS technology. In: Proceedings 34 th Design Automation Conference, June 1997, pp. 409–414 (1997)

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1. Sleep-Transistor Based Power-Gating Tradeoff Analyses;Lecture Notes in Computer Science;2013

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