A Low Power-Consumption Triple-Node-Upset-Tolerant Latch Design
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Link
https://link.springer.com/content/pdf/10.1007/s10836-022-05989-x.pdf
Reference27 articles.
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2. STTSRL: Design of Triple-Node Upset Self-Recovery Latch Based on Schmidt Trigger;Journal of Physics: Conference Series;2023-12-01
3. A triple-node-upset self-recoverable design based on Schmitt-triggers and C-elements;Microelectronics Reliability;2023-05
4. Hardened Latch Designs Based on the Characteristic of Transistor for Mitigating Multiple-Node-Upsets in Harsh Radiation Environments;2023
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