Analyzing Vulnerability of Asynchronous Pipeline to Soft Errors: Leveraging Formal Verification

Author:

Lodhi Faiq KhalidORCID,Hasan Syed Rafay,Hasan Osman,Awwad Falah

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Scalable Formal Framework for the Verification and Vulnerability Analysis of Redundancy-Based Error-Resilient Null Convention Logic Asynchronous Circuits;Journal of Low Power Electronics and Applications;2024-01-14

2. ζ: A Novel Approach for Mitigating Single Event Transient Effects in Quasi Delay Insensitive Logic;2023 28th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC);2023-07-16

3. Error Resilient Sleep Convention Logic Asynchronous Circuit Design;2023 21st IEEE Interregional NEWCAS Conference (NEWCAS);2023-06-26

4. Characterization of Program Behavior under Faulty Instruction Encoding;Scientific Programming;2022-02-07

5. Soft Error Tolerant Quasi-Delay Insensitive Asynchronous Circuits: Advancements and Challenges;2021 34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI);2021-08-23

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