Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Reference29 articles.
1. Baarir S, Braunstein C, Encrenaz E, Ilié J M, Mounier I, Poitrenaud D, Younes S (2011) Feasibility analysis for robustness quantification by symbolic model checking. Formal Methods in System Design 39(2):165–184. doi: 10.1007/s10703-011-0121-5
2. Cavada R, Cimatti A, Dorigatti M, Griggio A, Mariotti A, Micheli A, Mover S, Roveri M, Tonetta S (2014) The nuxmv symbolic model checker. In: Computer aided verification. springer, p 334–342
3. Dill DL (1998) What’s between simulation and formal verification?. In: Dac, vol 98, pp 328–329
4. Fant K, Brandt S (1996) Null convention logictm: a complete and consistent logic for asynchronous digital circuit synthesis. In: Proceedings of International Conference on Application Specific Systems, Architectures and Processors, 1996. ASAP 96, , pp 261–273. doi: 10.1109/ASAP.1996.542821
5. Fey G (2012) Mathematical and engineering methods in computer science: 7th international doctoral workshop, Memics 2011, Lednice, Czech Republic, october 14-16, 2011, revised selected papers. Springer Berlin Heidelberg, Berlin, Heidelberg, pp 47–56. chap Assessing System Vulnerability Using Formal Verification Techniques. doi: 10.1007/978-3-642-25929-6_4
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