Quaternary Quantum/Reversible Half-Adder, Full-Adder, Parallel Adder and Parallel Adder/Subtractor Circuits-Reference-Cited by-同舟云学术

Quaternary Quantum/Reversible Half-Adder, Full-Adder, Parallel Adder and Parallel Adder/Subtractor Circuits

Published:2019-04-12 Issue:7 Volume:58 Page:2184-2199
ISSN:0020-7748
Container-title:International Journal of Theoretical Physics
language:en
Short-container-title:Int J Theor Phys

Author:

Taheri Monfared Asma,Haghparast Majid^ORCID,Datta Kamalika

Publisher

Springer Science and Business Media LLC

Subject

Physics and Astronomy (miscellaneous),General Mathematics

Link

http://link.springer.com/content/pdf/10.1007/s10773-019-04108-5.pdf

Reference47 articles.

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3. Perkowski, M., Al-Rabadi, A., Kerntopf, P., Buller, A., Chrzanowska-Jeske, M., Mishchenko, A., Azad Khan, M., Coppola, A., Yanushkevich, S., Shmerko, V., Jozwiak, L.: A general decomposition for reversible logic. In: Proceedings of RM. 119–138 (2001)

4. Perkowski, M., Kerntopf, P.: Reversible logic. Invited tutorial. In: Proceedings of EURO MICRO (2001)

5. Babu, H. M. H., Chowdhury, A. R.: Design of a reversible binary coded decimal adder by using reversible 4-bit parallel adder. In 18th International Conference on VLSI Design Held Jointly with 4th International Conference on Embedded Systems Design, pp. 255–260. IEEE (2005)

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