An SOI-Based 3D Circuit Integration Technology
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Publisher
Springer US
Link
http://link.springer.com/content/pdf/10.1007/978-0-387-76534-1_8.pdf
Reference34 articles.
1. Burns JA, Aull BF, Chen CK, Chen CL, Keast CL, Knecht JM, Suntharalingam V, Warner K, Wyatt PW, Yost DRW (2006) A wafer-scale 3-D circuit integration technology. IEEE Trans Electron Devices 53(10):2507–2516.
2. McClelland RW, Bozler CO, Fan JCC (1980) TP-A2 the cleft process: a technique for producing many epitaxial single-crystal GaAs films by employing one reusable substrate. IEEE Trans Electron Devices 27(11):2188.
3. Sailer PM, Singhal P, Hopwood J, Kaeli DR, Zavracky PM, K. Warner K, Vu DP (1997) Creating 3D circuits using transferred films. IEEE Circuits Devices Mag 13(6):27–30.
4. Burns J, McIlrath L, Hopwood J, Keast C, Vu DP, Warner K, Wyatt P (2000) An SOI-based three-dimensional integrated circuit technology. In: IEEE international SOI conference proceedings, pp 20–21.
5. Burns J, McIlrath L, Keast C, Lewis C, Loomis A, Warner K, Wyatt P (2001) Three-dimensional integrated circuits for low-power, high-bandwidth systems on a chip. In: Digest of technical papers of IEEE international solid-state circuits conference, pp 268–269.
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