A PUF-Based Secure Boot for RISC-V Architectures-Reference-Cited by-同舟云学术

A PUF-Based Secure Boot for RISC-V Architectures

Published:2024 Issue: Volume: Page:87-94
ISSN:1876-1100
Container-title:Lecture Notes in Electrical Engineering
language:en
Short-container-title:

Author:

Di Matteo Stefano^ORCID,Zulberti Luca^ORCID,Lapenna Federico Cosimo,Nannipieri Pietro^ORCID,Crocetti Luca^ORCID,Fanucci Luca^ORCID,Saponara Sergio^ORCID

Publisher

Springer Nature Switzerland

Link

https://link.springer.com/content/pdf/10.1007/978-3-031-48121-5_13

Reference14 articles.

1. ARM security technology—Building a secure system using Trust Zone technology (2005–2009). https://developer.arm.com/documentation/PRD29-GENC-009492/c

2. Baldanzi L, Crocetti L, Di Matteo S, Fanucci L, Saponara S, Hameau P (2019) Crypto accelerators for power-efficient and real-time on-chip implementation of secure algorithms. In: 2019 26th IEEE international conference on electronics, circuits and systems (ICECS), pp 775–778. https://doi.org/10.1109/ICECS46596.2019.8964731

3. Di Matteo S, Lo Gerfo M, Saponara S (2023) Vlsi design and fpga implementation of an ntt hardware accelerator for homomorphic seal-embedded library. IEEE Access 11:72498–72508. https://doi.org/10.1109/ACCESS.2023.3295245

4. Gautschi MEA (2017) Near-threshold risc-v core with dsp extensions for scalable iot endpoint devices. IEEE Trans Very Large Scale Integr (VLSI) Syst 25(10):2700–2713. https://doi.org/10.1109/TVLSI.2017.2654506

5. Haj-Yahya J, Wong MM, Pudi V, Bhasin S, Chattopadhyay A (2019) Lightweight secure-boot architecture for risc-v system-on-chip, pp 216–223 (2019). https://doi.org/10.1109/ISQED.2019.8697657, https://www.scopus.com/inward/record.uri?eid=2-2.0-85065164064 &doi=10.1109%2fISQED.2019.8697657 &partnerID=40 &md5=dbd40305c40b567a1f6089561f3d8863 cited by: 17; All Open Access, Green Open Access