Publisher
Springer International Publishing
Reference21 articles.
1. Dabal, P., Pelka, R.: FPGA implementation of chaotic pseudo-random bit generators. In: Proceedings of the 19th International Conference Mixed Design of Integrated Circuits and Systems, MIXDES 2012, pp. 260–264. IEEE (2012)
2. Pande, A., Zambreno, J.: A chaotic encryption scheme for real-time embedded systems: design and implementation. Telecommun. Syst. 52(2), 551–561 (2013)
3. Azzaz, M., Tanougast, C., Sadoudi, S., Dandache, A.: Real-time FPGA implementation of Lorenz’s chaotic generator for ciphering telecommunications. In: 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, pp. 1–4. IEEE (2009)
4. de la Fraga, L.G., Torres-Pérez, E., Tlelo-Cuautle, E., Mancillas-López, C.: Hardware implementation of pseudo-random number generators based on chaotic maps. Nonlinear Dyn. 90(3), 1661–1670 (2017). https://doi.org/10.1007/s11071-017-3755-z
5. Lecture Notes in Computer Science (Lecture Notes in Artificial Intelligence);M De Bernardi,2019
Cited by
2 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献