Software-Defined FPGA Accelerator Design for Mobile Deep Learning Applications-Reference-Cited by-同舟云学术

Software-Defined FPGA Accelerator Design for Mobile Deep Learning Applications

Published:2019 Issue: Volume: Page:68-77
ISSN:0302-9743
Container-title:Lecture Notes in Computer Science
language:
Short-container-title:

Author:

Mousouliotis Panagiotis G.^ORCID,Petrou Loukas P.^ORCID

Publisher

Springer International Publishing

Link

http://link.springer.com/content/pdf/10.1007/978-3-030-17227-5_6

Reference14 articles.

1. Lecture Notes in Computer Science;KMA Ali,2017

2. Gschwend, D.: ZynqNet: an FPGA-accelerated embedded convolutional neural network. Master ETH-Zurich: Swiss Federal Institute of Technology Zurich (2016)

3. Guo, K., et al.: Angel-Eye: a complete design flow for mapping CNN onto embedded FPGA. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 37(1), 35–47 (2018)

4. Gysel, P., Pimentel, J., Motamedi, M., Ghiasi, S.: Ristretto: a framework for empirical study of resource-efficient inference in convolutional neural networks. IEEE Trans. Neural Netw. Learn. Syst. 99, 1–6 (2018)

5. Iandola, F., Keutzer, K.: Small neural nets are beautiful: enabling embedded systems with small deep-neural-network architectures. In: Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion. ACM (2017). Article no. 1

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