1. https://patents.google.com/patent/US8074110. Accessed 30 Dec 2022
2. https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/2nd-gen-xeon-scalable-datasheet-vol-1.pdf
3. Bienia, C., et al.: The PARSEC benchmark suite: characterization and architectural implications. In: PACT (2008)
4. Binkert, N., et al.: The Gem5 simulator. SIGARCH Comput. Archit. News 39, 1–7 (2011)
5. Cai, E., Marculescu, D.: Temperature effect inversion-aware power-performance optimization for FinFET-based multicore systems. IEEE TCAD 36, 1897–1910 (2017)