Author:
Muzaffar Shahzad,Elfadel Ibrahim Abe M.
Publisher
Springer International Publishing
Reference6 articles.
1. Q. Du, J. Zhuang, T. Kwasniewski, A 2.5 Gb/s, low power clock and data recovery circuit, in 20th Canadian Conference on Electrical and Computer Engineering (CCECE), Vancouver, BC, April 2007, pp. 526–529
2. M. Loh, A. Emami-Neyestanak, All-digital CDR for high-density, high-speed I/O, in 12th IEEE Symposium on VLSI Circuits (VLSIC’10), Honolulu, HI, June 2010, pp. 147–148
3. M. Loh, A. Emami-Neyestanak, A 3x9 Gb/s shared, all-digital CDR for high-speed, high-density I/O. IEEE J. Solid State Circuits 47(3), 641–651 (2012)
4. S. Muzaffar, I.M. Elfadel, IoT communication using dynamic edge-coded serial signaling. ACM Trans. Sen. Netw. 17(1), Article 8, 24 pp. (2021)
5. L.-K. Soh, W.-T. Wong, A 2.5-12.5 Gbps interpolator-based clock and data recovery circuit for FPGA, in 4th Asia Symposium on Quality Electronic Design (ASQED), Penang, July 2012, pp. 373–379